Cupertino, Calif. How do you design a 10-million-gate chip on a tight schedule? Not one gate at a time. Simon Bloch is president and CEO of Aristo Technology Inc., Cupertino, Calif. The recent winner ...

JTAG Technologies is aiming to widen the use of boundary scan test in design as well as production activities with a new set of downloadable tools which includes a free-for-life debug tool. Called ...