Design-Reuse

Andes Technology Announces RISC-V Single-core and Multicore Processors with DSP Instruction Set

Hsinchu, Taiwan, Mar. 12, 2019 – At the RISC-V Workshop Taiwan cohosted by Andes Technology today, Andes proudly announces the debut of its 32-bit A25MP and 64-bit AX25MP RISC-V multicore processors.
Design-Reuse

DSP Group and Endeavor Intertech Announce High Performance, Certified Accurate Instruction Set Simulation for TeakDSPCore

SAN JOSE, Calif., IP 2000 System-on-Chip Conference, March 20 -- Endeavor Intertech Corporation and DSP Group, Inc. announced today the launching of IPSim for Teak(TM), the new Certified Accurate ...
EDN

ARC instruction set

ARC's Tangent-core processor is unique among microcontrollers, but companies are starting to move their microcontroller offerings in Tangent's direction. The ARC core provides 30 base instructions, ...
Electronic Design

Instruction-Set Extensions Let CPU Accelerate Key Operations

The S5000 software-configurable processor family combines the flexibility of the compilable Tensilica Xtensa RISC processor core and the programmable Stretch instruction-set extension fabric (ISEF) to ...
EDN

2002 DSP directory

Last year was a harsh one for processor-device sales. According to market analysis from iSuppli (www.isuppli.com) and Forward Concepts (www.forwardconcepts.com), DSP sales were down 30 to 45%, ...
New Electronics

First working silicon of a DSP with embedded FPGA

Flex Logix Technologies, a supplier of reconfigurable computing solutions, architecture and software, and CEVA, a licensor of wireless, sensing and integrated IP solutions, have announced the first ...
Electronic Design

DSP Core Optimized For Physical-Layer Processing

To meet the high-speed broadband signal-processing requirements of emerging 3G wireless basestations, 3DSP has developed an advanced DSP core, the SP-20. Optimized for physical-layer signal processing ...
Stockhouse

FLEX LOGIX AND CEVA ANNOUNCE FIRST WORKING SILICON OF A DSP WITH EMBEDDED FPGA TO ALLOW A FLEXIBLE/CHANGEABLE ISA

Flex Logix® EFLX embedded FPGA brings reconfigurable computing to CEVA-X2 DSP instruction extension to support demanding and changing workloads MOUNTAIN VIEW, Calif., June 27, 2022 ...
New Electronics

Cadence unveils Tensilica Vision Q6 DSP IP

Cadence Design Systems has unveiled the Cadence Tensilica Vision Q6 DSP, its latest DSP for embedded vision and AI that has been built on a new, faster processor architecture. The fifth-generation ...
Business Wire

Xinyi Selects Cadence Tensilica Fusion F1 DSP for New Highly Integrated NB-IoT Modem

SHANGHAI--(BUSINESS WIRE)--MOBILE WORLD CONGRESS—Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Xinyi Information Technology, a leading narrowband (NB) internet of things (IoT) ...
Fox 5 San Diego

FLEX LOGIX AND CEVA ANNOUNCE FIRST WORKING SILICON OF A DSP WITH EMBEDDED FPGA TO ALLOW A FLEXIBLE/CHANGEABLE ISA

MOUNTAIN VIEW, Calif., June 27, 2022 /PRNewswire/ -- Flex Logix ® Technologies, Inc., the leading supplier of reconfigurable computing solutions, architecture and software, and CEVA, Inc. (NASDAQ: ...