Here are some of the highlights of the Linux 6.17 release: Specific support for single-core processors has been removed, and ...

What makes Efficient Computer’s Electron E1 stand out is the programmable nature of the system’s dataflow. The chip has a ...

Tenstorrent, the Toronto-based chip company led by veteran semiconductor architect Jim Keller, has partnered with Singapore’s ...

The collaboration unites Tenstorrent’s cutting-edge RISC-V CPU IP with CoreLab Technology’s highly efficient processor IP and SoC innovations. The outcome is Atlantis, an open-architecture compute ...

Backed by a comprehensive software ecosystem—including SDKs, unified GCC/LLVM-based toolchains, and IDEs—this RISC-V IP Cores portfolio enables rapid development and deployment across a wide range of ...

SiFive launched its 2nd Generation Intelligence™ family, featuring five new RISC-V-based products designed to accelerate AI ...

CHERI is seen as representing a transformative hardware security architecture that’s been designed to mitigate memory safety ...

Renesas Electronics Corporation has introduced the RA8T2 microcontroller group designed for motor control applications in ...

EnSilica, the ASIC specialist, and Codasip, a provider of functionally-safe and cyber-resilient RISC-V CPUs, will enable ...

A new technical paper titled “Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions” was published by researchers at Tampere University. Abstract “Custom instruction ...

The researchers "conclude that at least 40% of the x86 ISA, even after excluding multimedia extensions, could be emulated ...

EnSilica and Codasip announce a strategic partnership to enable custom ASICs incorporating CHERI to key sectors.